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ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 1 of 27 1 - 888 - 824 - 4184 ia 7 0c20 8 - bit microc ontroller data sheet
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 2 of 27 1 - 888 - 824 - 4184 copyright 2008 by innovasic semiconductor, inc. published by innovasic semiconductor, inc. 3737 princeton drive ne, suite 130, albuquerque, nm 87107 fido ? , fi do1100 ? , and spider are trademarks of innovasic semiconductor, inc. i2c ? bus is a trademark of philips electronics n.v. motorola is a registered trademark of motorola, inc.
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 3 of 27 1 - 888 - 824 - 4184 table of contents 1. features ................................ ................................ ................................ ................................ ..... 4 2. description ................................ ................................ ................................ ................................ 5 2.1 cpu ................................ ................................ ................................ ............................... 6 2.2 port a ................................ ................................ ................................ ............................ 6 2.3 port b ................................ ................................ ................................ ............................ 6 2.4 port c ................................ ................................ ................................ ............................ 7 2.5 port d ................................ ................................ ................................ ............................ 7 2.6 interrupt controller ................................ ................................ ................................ ....... 7 2.7 clock controller ................................ ................................ ................................ ............ 7 2.8 perf file ................................ ................................ ................................ ......................... 7 2.9 timer ................................ ................................ ................................ ............................. 7 2.10 rom ................................ ................................ ................................ .............................. 7 3. addressing modes ................................ ................................ ................................ .................. 10 3.1 single - register addressing mode ................................ ................................ .............. 11 3.2 dual - register addressing mode ................................ ................................ ................. 12 3.3 peripheral - fil e addressing mode ................................ ................................ ............... 13 3.4 immediate addressing mode ................................ ................................ ...................... 13 3.5 program counter relative addressing mode ................................ ............................. 14 3.6 direct memory addressing mode ................................ ................................ .............. 15 3.7 register - file indirect addressing mode ................................ ................................ ..... 15 3.8 indexed addressing mode ................................ ................................ .......................... 16 4. instruction overview ................................ ................................ ................................ .............. 16 5. dc characteristics ................................ ................................ ................................ .................. 24 6. ac characteristics ................................ ................................ ................................ .................. 25 7. 70cx0 errata ................................ ................................ ................................ ........................... 27 8. revision history ................................ ................................ ................................ ..................... 27
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 4 of 27 1 - 888 - 824 - 4184 1. features ? pin - for - pin compatible with texas instruments tms70c20 cmos 8 - bit microcontrol ler. ? register - to - register architecture. ? up to 4k bytes on - chip rom. ? 128 bytes internal ram. ? 13 - bit timer. ? memory - mapped ports for easy adressing. ? eight addressing form ats. ? single - instruction bcd add and subtract. ? two external maskable interrupts. ? two power - down modes. wake - up (160 ?a at 1 mhz typical) halt, xtal/clkin = gnd (1 ?a typical) ? cmos technology. ? operating voltage: 5v + / - 10 %. ? operating temperature: industrial range ( - 40 o c to +85 o c). ? maximum osc frequency: 5 mhz. ? available packages: 44 - pin plastic leaded chip carrier packa ge (plcc). 40 - pin, 600 mil, dual in - line package (dip). the ia70cx0 is a form, fit, and function replacement for the original texas instruments tms70cx0 cmos 8 - bit microcontroller. the ia70cx0 incorporates a cpu, memory, bit i/ o, timer, interrupts and external bus interface logic on a single chip. typical applications for the ia70cx0 microcontroller include industrial, consumer, computer, telecom and automo tive applications. innovasic?s version of the microcontroller includes all the features listed above and is plug and play with the original texas instruments device. innovasic produces replacement ics using its miles tm , or managed ic lifetime extension system, cloning technology. this technology produces replacement ics far more complex than "em ulation" while ensuring they are compatible with the original ic. miles tm captures the design of a clone so it can be produced even as silicon technology advances. miles tm also verifies the clone against the original ic so that even the "undocumented fea tures" are duplicated.
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 5 of 27 1 - 888 - 824 - 4184 2. description the IA70C20 microcontroller replaces obsolete ti tms70c20 devices, allowing customers to retain existing board designs, software compilers/assemblers, and emulation tools, thereby avoiding expensive redesign efforts . a block diagram of the 70c20 microcontroller is depicted in figure 1. figure 1. IA70C20 block diagram
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 6 of 27 1 - 888 - 824 - 4184 the 70c20 microcontroller consists of the following functional blocks: cpu port a port b port c port d interrupt control ler clock controller perf file timer rom a brief description of each block follows: 2.1 cpu the cpu block contains the microcode sequencer, the alu, and the cpu registers. the microcode sequencer controls the process of reading and executing the microcode that enables the IA70C20 to execute assembly code. the alu performs all of the logical and arithmetical operations for the device as required by the microcode. the cpu registers block contains basic information about the function of the IA70C20. the tw o registers are the 16 bit program counter (pc) and the 8 bit stack pointer (sp). 2.2 port a port a is an 8 bit input only port. pin a7 has a second function as the clock for the on - chip timer/event counter. 2.3 port b port b is an 8 - bit output port. pins b3 - b0 are general purpose bits while pins b7 - b4 are dual function pins. when in single - chip mode these pins are general purpose bits, otherwise they are bus control bits.
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 7 of 27 1 - 888 - 824 - 4184 2.4 port c in single - chip mode, port c is an 8 - bit bi - directional port in which ea ch pin may be individually set to be either an input or an output under the control of software. in all other modes, port c becomes a multiplexed address/data port for the off - chip memory bus providing the least significant byte of a 16 - bit address. 2.5 port d i n either single - chip or peripheral expansion mode, port d is an 8 - bit bi - directional port in which each pin may be individually set to be either an input or an output under the control of software. in either full expansion or microprocessor mode, por t d contains the most significant byte of the 16 - bit address. 2.6 interrupt controller there are four interrupt levels int0 - int3, with int0 having the highest priority. this block receives the external interrupt and alerts the cpu, enabling servicing of the interrupt. the interrupts are synced to the positive edge of x2_div_2, the divided clock. 2.7 clock controller generates two enable pulse signals, one at ? x2, and one at 1/16 x2, to clock internal registers at varying speeds. 2.8 perf file contains regist er file registers, data holding registers, and peripheral registers for port operations. 2.9 timer a programmable timer/event counter. it is an 8 bit modulo - n counter with a programmable pre - scaled clock source. int2 is an internal interrupt used by the timers. 2.10 rom customer specific 2k x 8 instruction rom.
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 8 of 27 1 - 888 - 824 - 4184 hexadecimal instruction table/opcode map high 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 a 1011 b 1100 c 1101 d 1110 e 1111 f low 0000 0 nop movp pn,a tsta/ clrc mov a,b mov a,rn jmp trap 15 0001 1 idle movp pn,b tstb mov b,rn jn/ jlt trap 14 0010 2 mov rn,a mov %n,a mov rn,b mov rn,rn mov %,n,b mov b,a mov %n,pn movp a,pn movp pn,b movp %n,pn dec a dec b dec rn jz/ jeq trap 1 3 0011 3 and rn,a and %n,a and rn,b and rn,rn and %,n,b and b,a and %n,pn andp a,pn andp b,pn andp %n,pn inc a inc b inc rn jc/ jhs trap 12 0100 4 or rn,a or %n,a or rn,b or rn,rn or %,n,b or b,a or %n,r orp a,pn orp b,pn orp %n,pn inv a inv b inv rn jp/ jgt trap 11 0101 5 eint xor rn,a xor %n,a xor rn,b xor rn,rn xor %,n,b xor b,a xor %n,r xorp a,pn xorp b,pn xorp %n,pn clr a clr b clr rn jpz/ jge trap 10 0110 6 dint btjo rn,a btjo %n,a btjo rn,b btjo rn,rn btjo %,n,b btjo b,a btjo %n,r btjop a,p n btjop b,pn btjop %n,pn xchb a xchb b xchb rn jnz/ jne trap 9 0111 7 setc btjz rn,a btjz %n,a btjz rn,b btjz rn,rn btjz %,n,b btjz b,a btjz %n,r btjzp a,pn btjzp b,pn btjzp %n,pn swap a swap b swap rn jnc/ jl trap 8 1000 8 pop st add rn,a add %n,a ad d rn,b add rn,rn add %,n,b add b,a add %n,r movd %n,rn movd rn,rn movd %n,(b), rn push a push b push rn trap 23 trap 7 1001 9 stsp adc rn,a adc %n,a adc rn,b adc rn,rn adc %,n,b adc b,a adc %n,r pop a pop b pop rn trap 22 trap 6 1010 a rets sub rn,a sub %n,a sub rn,b sub rn,rn sub %,n,b sub b,a sub %n,r lda @n lda *rn lda @n(b) djnz a dinz b dinz rn trap 21 trap 5 1011 b reti sbb rn,a sbb %n,a sbb rn,b sbb rn,rn sbb %,n,b sbb b,a sbb %n,r sta @n sta *rn sta @n(b) decd a decd b decd rn trap 20 trap 4 1100 c mpy rn,a mpy %n,a mpy rn,b mpy rn,rn mpy %,n,b mpy b,a mpy %n,r br @n br *rn br @n(b) rr a rr b rr rn trap 19 trap 3 1101 d ldsp cmp rn,a cmp %n,a cmp rn,b cmp rn,rn cmp %,n,b cmp b,a cmp %n,r cmpa @n cmpa *rn cmpa @n(b) rrc a rrc b rrc rn t rap 18 trap 2 1110 e push st dac rn,a dac %n,a dac rn,b dac rn,rn dac %,n,b dac b,a davc %n,r call @n call *rn call @n(b) rl a rl b rl rn trap 17 trap 1 1111 f dsb rn,a dsb %n,a dsb rn,b dsb rn,rn dsb %,n,b dsb b,a dsb %n,r rlc a rlc b rlc rn trap 16 trap 0 a - register a rn - register file register %n - immediate addressing *rn - indirect addressing b - register a pn - peripheral file register @n - direct addressing
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 9 of 27 1 - 888 - 824 - 4184 signal pin i/o description plcc dip a0 a1 a2 a3 a4 a5 a6 a7/ec1 7 8 9 10 11 18 16 12 6 7 8 9 10 16 15 11 i i i i i i i i port a. all pins may be used as high - impedance input - only lines. pin a7/ec1 may also be used as the timer/event counter input. b0 b1 b2 b3 b4/alatch b5/r/w b6/enable b7/clkou t 3 4 5 41 42 1 43 2 3 4 5 37 38 1 39 2 o o o o o o o o port b. b0 - b7 are general - purpose output - only pins. b4 - b7 become memory - expansion control signals in peripheral - expansion, full - expansion, and microprocessor modes. data output/memory interface addr ess latch strobe. data output/memory read/write signal. data output/memory interface enable strobe. data output/internal clockout. c0 c1 c2 c3 c4 c5 c6 c7 31 32 33 34 35 36 37 38 28 29 30 31 32 33 34 35 i/o i/o i/o i/o i/o i/o i/o i/o port c. c0 - c7 can be individually selected in software as general - purpose input or output pins in single - chip mode. c0 - c7 become the lsb address/data bus in peripheral - expansion, full - expansion, and microprocessor modes. d0 d1 d2 d3 d4 d5 d6 d7 30 29 27 26 25 24 22 21 27 2 6 24 23 22 21 20 19 i/o i/o i/o i/o i/o i/o i/o i/o port d. d0 - d7 can be individually selected in software as general - purpose input or output pins in single - chip or peripheral - expansion modes. d0 - d7 become the msb address/data bus in full - expansion and m icroprocessor modes. int1 14 13 i highest priority maskable interrupt int3 13 12 i lowest priority maskable interrupt reset 15 14 i device reset mc 40 36 i mode control pin, vcc for microprocessor mode xtal2/clkin 19 17 i crystal input for control of internal oscillator xtal1 20 18 o crystal ouput for control of internal oscillator vcc 28 25 supply voltage (positive) vss 44 39 23 40 ground reference * also apply to se70cp160a prototyping device.
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 10 of 27 1 - 888 - 824 - 4184 3. addressing modes IA70C20 a ssembly language supports eight addressing modes. these eight modes are listed in table 1. a description of each mode follows the table. table 1. IA70C20 addressing modes addressing mode example single register label dec b inc r45 clr r23 dual register label mov b , a add a , r17 cmp r32 , r73 peripheral file label xorp a , r17 movp p42 , b immediate la bel and %>c5 , r55 andp %value , p32 btjo %>d6 , r80 , label b 5 / r / w _ n v ss b 7 / clkout b 0 / t 2 out b 1 / t 1 out b 2 a 0 a 1 a 2 a 3 a 4 / sclk a 7 / ec 1 int 3 _ n int 1 _ n reset _ n a 6 / ec 2 a 5 / rxd xtal 2 / clkin xtal 1 d 7 d 6 b 6 / enable _ n b 4 / alatch b 3 / txd mc c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 0 d 1 v cc d 2 d 3 d 4 d 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 15 16 17 18 19 20 26 25 24 23 22 21 28 29 30 31 32 33 34 35 36 37 38 39 40 a 1 a 2 a 3 a 4 / sclk a 7 / ec 1 int 3 _ n int 1 _ n reset _ n a 6 / ec 2 a 5 / r x d x t a l 2 / c l k i n 8 9 10 11 12 13 14 15 16 17 b 6 / e n a b l e _ n b 4 / a l a t c h b 3 / t x d m c c 7 c 6 c 5 c 4 c 3 c 2 c 1 29 30 31 32 33 34 35 36 37 38 39 7 b 5 / r / w _ n b 7 / c l k o u t b 0 / t 2 o u t b 1 / t 1 o u t b 2 n c 18 19 20 x t a l 1 d 7 d 6 a 0 nc 27 26 25 24 23 22 21 28 1 2 3 4 5 6 40 41 42 43 44 v s s v ss c 0 d 0 d 1 v c c d 2 d 3 d 4 d 5 v s s a . plastic 40 - pin dip b . 44 - pin plcc u
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 11 of 27 1 - 888 - 824 - 4184 program counter relative label 1 jmp label djnz a , label btjo %>16 , r12 , label btjop b , p7 , label direct memory label lda @>f3d4 cmpa @label register file indirect label sta *r43 indexed label 2 br @label (b) 3.1 single - register addressing mode in single - register addressing mode, a single register denoted by rn (n is the register file number in the range 0 - 127) containing an eight - bit operand is used. a and b can denote r0 and r1, respectively. figure 1 illustrates the object code generated by a single operand instruction for the following cases:
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 12 of 27 1 - 888 - 824 - 4184 figure 1. single - register addressing mode object code case 1 case 2 (pc) (pc) (pc + 1) case 1 a b case 2 rn 3.2 dual - register addressing mode in dual register addressing m ode, instructions use a source and a destination register that each contain 8 - bit operands. the source register is always listed prior to the destination register in the assembly language. figure 2 illustrates the byte requirements for all dual addressin g mode instructions. figure 2. dual - register addressing mode byte requirements destination destination source a b iop rs a b rd source a b iop rs a b rd 1 2 2 3 1 2 1 3 2 2 3 2 2 3 2 2 3 2 2 3 bytes needed for bytes needed for move instructions all other instructions opcode opcode rn
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 13 of 27 1 - 888 - 824 - 4184 3.3 peripheral - file addressing mode in peripheral - file addressing mode, instructions perform i/o tasks. each pf register is an 8 - bit port that can be referred to as pn. four instructions use peripheral - file add ressing mode: ? movp, ? andp, ? orp, and ? xorp. these instructions may use register a or b as the source register and pn as the destination register. movp may also be executed using pn as the source register and a or b as the destination register. (btjop and b tjzp are also peripheral - file instructions but they have a different format.) figure 3 illustrates the byte requirements of the instructions using the peripheral - file addressing mode. figure 3. peripheral - file addressing mode byte requirements destination destination source a b iop ps a b pd source a b iop pd 2 3 2 3 3 4 2 2 bytes needed for bytes needed for andp, orp, and movp all btjop and btjzp 3.4 immediate addressing mode in immediate addressing mode instructions use an immediate eight - bit operand. either a constant value or a label preceded by a percent sign (%) can be used as the immediate value. the movd instruction uses 16 - bit immediate operands in two special formats. figure 4 illustrates the simplest case of an instruction using this mode.
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 14 of 27 1 - 888 - 824 - 4184 figure 4. immediate addressing mode object code (pc) ? (pc + 1) ? 3.5 program counter relative addressing mode all jump instructions use program counter relative addressing m ode. a target address (ta) must be included in any assembly language jump instruction. the offset is calculated as follows: offset = ta C pcn , where pcn is the location of the next instruction and C 128 < ta < 127. figure 5 illustrates object code genera ted by a jump instruction. figure 5. program counter relative addressing mode object code (pc) : n b y t e s (pc + n) opcode iop d s offset opcode iop
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 15 of 27 1 - 888 - 824 - 4184 3.6 direct memory addressing mode the operand for a direct addressing mode instruction is located in memory. the location is indicated by a 16 - bit address. the 16 - bit address is preceded by an @ sign and can be written as a constant value or as a label. figure 6 shows how the object code produced by an instruction using the direct memory addressing mode generates a 16 - bit effective address. figure 6. direct memory addressing mode object code (pc) (pc + 1) 16 - bi t effective address (pc + 2) 3.7 register - file indirect addressing mode a register pair containing a 16 - bit effective address is used in register file indirect addressing mode. the indirect register file address is written as a register number ( rn) preceded by an asterisk (*), that is, *rn. the lsb of the address is contained in rn, and the msb of the address is contained in the previous register (rn - 1). figure 7 shows how the object code produced by an instruction using register file indirect addressing mode generates a 16 - bit effective address. opcode addr msb addr lsb
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 16 of 27 1 - 888 - 824 - 4184 + figure 7. register - file indirect addressing mode object code (pc) rn - 2 rn - 1 (pc + 1) rn rn rn+1 3.8 indexe d addressing mode in indexed addressing mode, a 16 - bit address formed by adding the contents of the b register to a 16 - bit direct memory address is used to access the operand. the assembly language statement for the indexed addressing mode contains the d irect memory address written as a 16 - bit constant value or a label, preceded by an @ sign and followed by a b in parentheses: @label(b). the addition automatically transfers any carries into the msb. figure 8 illustrates how the object code produced by a n instruction using the indexed addressing mode generates a 16 - bit effective address. figure 8. indexed addressing mode object code (pc) (pc + 1) (pc + 2) 4. instruction overview following is a listing of assembly language instructions for the IA70C20. labels, mnemonics, operands, and comments must be separated by at least one space in the assembly code: tms7000 family instruction overview mnemonic opcode bytes cycles tc(c) status c n z i operation description adc b,a rs,a rs,b rs,rd %iop,a %iop,b 69 19 39 49 29 59 1 2 2 3 2 2 5 8 8 10 7 7 r r r x (s) + (rd) + (c) ? (rd) add the source, destination, and carry bit together. store at the destination. opcode rn 16 - bit effective address 1.1.1.1 op co de addr msb addr lsb reg b index 16 - bit effective address
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 17 of 27 1 - 888 - 824 - 4184 %iop,rd 79 3 9 add b,a rs,a rs,b rs,rd %iop,a %iop,b %iop,rd 68 18 38 48 28 58 78 1 2 2 3 2 2 3 5 8 8 10 7 7 9 r r r x (s) + (rd) ? (rd) add the source and destination operands at the destination address. and b,a rs,a rs,b rs,rd %iop,a %iop,b %iop,rd 63 13 33 43 23 53 73 1 2 2 3 2 2 3 5 8 8 10 7 7 9 0 r r x (s) and (rd) ? (r d) and the source and destination operands together and store at the destination address. andp a,pd b,pd %iop,pd 83 93 a3 2 2 3 10 9 11 0 r r x (s) and (pd) ? (pd) and the source and destination operands together and store at the destination address. note: add two to cycle count if branch is taken legend: 0 status bit set always to 0. 1 status bit set always to 1 r status bit set to a 1 or a 0 depending on results of operation. x status bit not affected. b bit ( ) affected. ofst offse t
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 18 of 27 1 - 888 - 824 - 4184 tms7000 family instruction overview (continued) mnemonic opcode bytes cycles tc(c) status c n z i operation description br @label @label(b) *rn 8c ac 9c 3 3 2 10 12 9 x x x x (xaddr) ? (pc) the pc will be replac ed with the contents of the destination operand. (1) btjo b,a,ofst rn,a,ofst rn,b,ofst rn,rd,ofst %iop,a,ofst %iop,b,ofst %iop,rn,ofst 66 16 36 46 26 56 76 2 3 3 4 3 3 4 7 (9) 10 (12) 10 (12) 12 (14) 9 (11) 9 (11) 11 (13) 0 r r x if (s [bit x]) and (rn [bit x]) 0, then (pc) + offset ? (pc) if the and of the source and destination operands 0, the pc will be modified to include the offset. (1) bjop a,pn,ofst b,pn,ofst %>iop,pn,ofst 86 96 a6 3 3 4 11 (13) 10 (12) 12 (14) 0 r r x if (s [bit x]) and (pn [bit x]) 0, then (pc) + offset ? (pc) if the and of the source and destination operands 0, the pc will be modified to include the offset. (1 ) btjz b,a,ofst rn,a,ofst rn,b,ofst rn,rf,ofst %>iop,a,ofst %>iop,b,ofst %>iop,rn,ofst 67 17 37 47 27 57 77 2 3 3 4 3 3 4 7 (9) 10 (12) 10 (12) 12 (14) 9 (11) 9 (11) 11 (13) 0 r r x if (s [bit x]) and not(rn [bitx]) 0, then (pc) + offset ? (pc) if the and of the source and not(destination) operands 0, the pc will be modified to include the offset. (1) btjzp a,pn,ofst b,pb,ofst %>iop,pb,ofst 87 97 a7 3 3 4 11 (13) 10 (12) 12 (14) 0 r r x if (s [bit x]) and not(pn [bitx]) 0, then (pc) + offset ? (pc) if the and of the source and not(destination) operands 0, the pc will be modified to include the offset. call @label @label(b) *rn 8e ae 9e 3 3 2 14 16 13 x x x x (sp) + 1 ? (sp) (pc msb) ? ((sp)) (sp) + 1 ? (sp) (pc lsb) ? ((sp)) (xaddr) ? (pc) clr a b rd b5 c5 d5 1 1 2 5 5 7 0 0 1 x 0 ? (rd) clear the destination operand. clrc b0 1 6 0 r r x 0 ? (c) clears the carry bit. note: add two to cycle count if branch is taken legend: 0 status bit set always to 0. 1 status bit set always to 1 r status bit set to a 1 or a 0 depending on results of operation. x status bit not affected. b bit ( ) affected. ofst offset
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 19 of 27 1 - 888 - 824 - 4184 tms7000 family instruction overview (continued) mnemonic opcode bytes cycles tc(c) status c n z i operation description cmp b,a rn,a rn,b rn,rn %iop,a %iop,b %iop,rn 6d 1d 3d 4d 2d 5d 7d 1 2 2 3 2 2 3 5 8 8 10 7 7 9 r r r x (rn) C (s) computed but not stored set flags on the result of the s ource operand subtracted from the destination operand. cmpa @label @label(b) *rn 8d ad 9d 3 3 2 12 14 11 r r r x (a) C (xaddr) computed but not stored set flags on result of the source operand subtracted from a. dac b,a rs,a rs,b rs,rd %>iop,a %>iop,b %>iop,rd 6e 1e 3e 4e 2e 5e 7e 1 2 2 3 2 2 3 7 10 10 12 9 9 11 r r r x (s) + (rd) + (c) ? (rd) (bcd) the source, destination, and the carry bit are added, and the bcd sum is stored at the destination address. contents on the s + rd operands initially need to be the bcd. dec a b rd b2 c2 d2 1 1 2 5 5 7 r r r x (rd) C 1 ? (rd) decrement destination operand by 1. decd a b rp bb cb db 1 1 2 9 9 11 r r r x (rd) C 1 ? (rp) decrement register pair by 1.c=0 on 0 C ffff transition dint 06 1 5 0 0 0 0 0 ? (global interrupt enable bit). clear the i bit. (1) djnz a,ofst b,ofst rd,ofst ba ca da 1 2 2 7 (9) 7 (9) 9 (11) x x x x (rd) C 1 ? (rd); if (rd) 0, (pc) + offset ? (pc) dsb b,a rs,a rs,b rs,rd %>iop,a %>iop,b %>iop,rd 6f 1f 3f 4f 2f 5f 7f 1 2 2 3 2 2 3 7 10 10 12 9 9 11 r r r x (rd) C (s) C 1 + (c) ? (rd) (bcd) the source of the operand is subtracted from the destination; this sum is then reduced by 1 and the carry bit is then added to it. the result is st ored as a bcd number. contents on the s + rd operands initially need to be bcd. eint 05 1 5 1 1 1 1 2 ? (global interrupt enable bit). 3 set the i bit. idle 01 1 6 x x x x (pc) ? (pc) until interrupt (pc) + 1 ? (pc) after return from interrupt stops c ex ecution until an interrupt. note: add two to cycle count if branch is taken legend: 0 status bit set always to 0. 1 status bit set always to 1 r status bit set to a 1 or a 0 depending on results of operation. x status bit not affected. b bit ( ) affected. ofst offset
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 20 of 27 1 - 888 - 824 - 4184 tms7000 family instruction overview (continued) mnemonic opcode bytes cycles tc(c) status c n z i operation description inc a b rd b3 c3 d3 1 1 2 5 5 7 r r r x (rd) + 1 ? ? 1?s complement the destination operand. ? ? ? ? load sp with register b?s contents. ? ? ? ? note: add two to cycle count if branch is taken legend: 0 status bit set always to 0. 1 status bit set always to 1 r status bit set to a 1 or a 0 depending on results of operation. x status bit not affec ted. b bit ( ) affected. ofst offset
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 21 of 27 1 - 888 - 824 - 4184 tms7000 family instruction overview (continued) mnemonic opcode bytes cycles tc(c) status c n z i operation description mpy b,a rs,a rs,b rn,rn %>iop,a %>iop,b %>iop,rn 6c 1c 3c 4c 2c 5c 7c 1 2 2 3 2 2 3 44 47 47 49 46 46 48 0 r r x (s) x (rn) ? ? ? ? ? C ? ? C ? ? ? ? ? ? C ? ? C ? ? C ? ? C ? ? C ? note: add two to cycle count if branch is taken legend: 0 status bit set always to 0. 1 status bit set always to 1 r status bit set to a 1 or a 0 depending on results of operation. x status bit not affected. b bit ( ) affected. ofst offset
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 22 of 27 1 - 888 - 824 - 4184 tms7000 family instruction overview (continued) mnemonic opcode bytes cycles tc( c) status c n z i operation description rl a b rd be ce de 1 1 2 5 5 7 b7 r r x bit(n) ? bit(n + 1) bit(7) ? bit(0) and carry rlc a b rd bf cf df 1 1 2 5 5 7 b7 r r x bit(n) ? bit(n + 1) c arry ? bit(0) but(7) ? carry rr a b rd bc cc dc 1 1 2 5 5 7 b0 r r x bit(n +1) ? bit(n) bit(0) ? bit(7) and carry rrc a b rd bd cd dd 1 1 2 5 5 7 b0 r r x bit(n +1) ? bit(n) c arry ? bit(7) bit(0) ? carry sbb b,a rs,a rs,b rs,rd %>iop,a %>iop,b %>iop,rd 6b 1b 3b 4b 2b 5b 7b 1 2 2 3 2 2 3 5 8 8 10 7 7 9 r r r x (rd) C (s) C 1 + (c) ? (rd) des tination minus source minus 1 plus carry; stored at the destination address. setc 07 1 5 1 0 1 x 1 ? (c) set the carry bit. sta @label @label(b) *rd 8b ab 9b 3 3 2 11 13 10 0 r r r x (a) ? (xaddr) store a at the destination. stsp 09 1 6 x x x x (sp) ? (b) copy the sp into register b. sub b,a rs,a rs,b rs,rd %>iop,a %>iop,b %>iop,rd 6a 1a 3a 4a 2a 5a 7a 1 2 2 3 2 2 3 5 8 8 10 7 7 9 r r r x (rd) C (s) ? (rd) store the destination operand minus the source operand into the destination. swap a b rn b7 c7 d7 1 1 2 8 8 10 r r r x rd(hn,ln) ? rd(ln,hn) swap the operand?s hi and lo nibbles. trap 0 - 23 e8 - ff 1 14 x x x x (sp) + 1 ? (sp) (pc msb) ? ((sp)) (sp) +1 ? (sp) (pc lsb) ? ((sp)) (entry vector) ? (pc) note: add two to cycle count if branch is taken legend: 0 status bit set always to 0. 1 status bit set always to 1 r status bit set to a 1 or a 0 depending on results of operation. x status bit not affected. b bit ( ) affected. ofst offset
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 23 of 27 1 - 888 - 824 - 4184 tms7000 family instruction overview (continued) mnemonic opcode bytes cycles tc(c) status c n z i operation description tsta b0 1 6 0 r r x 0 ? (c) set carry bit; set sign and zero flags on the value of register a. tstb c1 1 6 0 r r x 0 ? (c) set carry bit; set sign and zero flags on the value register b. xchb a rn b6 d6 1 2 6 8 0 r r x (b) ? ? (rn) swap the contents of register b with (d). xor b,a rs,a rs,b rs,rd %>iop,a %>iop,b %>iop,rd 65 15 35 45 25 55 75 1 2 2 3 2 2 3 5 8 8 10 7 7 9 0 r r x (s) xor (rd) ? (rd) logically exclusive or the source and destination operands, store at the destination address. xorp a,pd b,pd %>iop,pd 85 95 a5 2 2 3 10 9 11 0 r r x (s) xor (pd) ? (pd) logically exclusive or the source and destination operands, store at the destinati on. note: add two to cycle count if branch is taken legend: 0 status bit set always to 0. 1 status bit set always to 1 r status bit set to a 1 or a 0 depending on results of operation. x status bit not affected. b bit ( ) affected. ofst offset
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 24 of 27 1 - 888 - 824 - 4184 5. dc characteristics ta = - 40 c to ta = 85 c, supply voltage = 4.5v to 5.5vdc unless otherwise specified. parameter symbol conditions limits unit min max input voltage high vih all except int1, int3, reset_n 0.7*vcc vcc+0.3 v input voltage low vil all except int1, int3, reset_n vcc - 0.3 0.3*vcc v input voltage high vih int1, int3, reset_n 3.22 vcc+0.3 v input voltage low vil int1, int3, reset_n vcc - 0.3 1.84 v input capacitance ci not tested - guaranteed by process - 4 pf output voltage high voh ioh = 6ma vcc - 0.5 - v ioh = 24ma output voltage low vol iol = 10ma vcc - 2.0 - v supply current icc vcc = 5v, fosc(min) 1.35mhz fosc(max) = 5mhz 9.4 35.0 ma wake up current iccwu not measured - - - halt current device clk active icch not measured - - - halt current device clk stopped icchs not measured - - - input leakage current icchs vcc = 5v - < 10 ua tri - state leakage current ii 4.5 < vcc < 5.5 - 10 ua low voltage operation itsl normal operating conditions 4.5 5.5 v
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 25 of 27 1 - 888 - 824 - 4184 6. ac characteristics ta = - 40 c to ta = 85 c, supp ly voltage = 4.5v to 5.5 vdc unless otherwise specified. reference figures 3.4.2.2,3.4.2.3,3.4.2.4,3.4.2.5, for interface timing relationships. parameter symbol conditions limits unit min max rc network frequency fosc r = 15k, c = 47pf, 1.4 2.1 mhz rc network osc input vihrc 0.7*vcc - v vilrc - 0.3*vcc v rc clock to clkouta delay td rtest = 1k, ctest = 1pf 28 ns clockout external cycle time tc( c) tc( c) = 2/fosc 952 1481 clock internal state cycle time tc(s) tc(s) = 2/fosc 952 1481 c rystal cycle time tc(p) tc(p) = 1/fosc 741 476 clockin pulse width high tf 45% to 55% of 1/fosc 333 214 clockin pulse width low tw 55% to 45% of 1/fosc 333 214 clockout pulse width high tw(ch) caution! this device is to be used in the s ingle chip mode only. other operating modes are used for functional testing purposes. these characteristics would be used for expansion (memory) modes and are not applicable to the single chip mode. clockout pulse width low tw(cl) clockout r ise to alatch fall td(ch - jl) alatch pulse width high tw(jh) address valid high before alatch fall td(ah - jl) address valid low before alatch fall td(al - jl) address hold low before alatch fall th(jl - al) r/w valid befor e alatch fall td(rw - jl)
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 26 of 27 1 - 888 - 824 - 4184 signal name req. setup time measured setup time req. hold time measured hold time req. clock to out measured clock to out pa_0 80 1.38 70 1.38 na na pa_1 80 1.35 70 1.35 na na pa_2 80 1.33 70 1.33 na na pa_ 3 80 1.29 70 1.29 na na pa_4 80 1.22 70 1.22 na na pa_5 80 1.15 70 1.15 na na pa_6 80 1.14 70 1.14 na na pa_7 80 1.19 70 1.19 na na pb_0 na na na na 100 24.27 pb_1 na na na na 100 24.33 pb_2 na na na na 100 24.31 pb_3 na na na na 100 24.28 pb_4 na na na na 100 25.83 pb_5 na na na na 100 25.95 pb_6 na na na na 100 25.71 pb_7 na na na na 100 26.68 pc_0 80 39.06 70 39.06 100 56.05 pc_1 80 36.01 70 38.15 100 56.91 pc_2 80 38.3 70 38.74 100 56.54 pc_3 80 36.42 70 38.53 100 56.35 pc_4 80 39.91 70 39.91 100 57.27 pc_5 80 39.81 70 39.94 100 57.77 pc_6 80 39.14 70 39.99 100 58.28 pc_7 80 39.26 70 39.26 100 56.53 pd_0 80 1.18 70 1.18 100 26.27 pd_1 80 1.15 70 1.15 100 26.13 pd_2 80 1.13 70 1.13 100 26.03 pd_3 80 1.13 70 1.13 100 26.1 pd_4 80 1 .14 70 1.14 100 26.09 pd_5 80 1.16 70 1.16 100 26.09 pd_6 80 1.15 70 1.15 100 26.44 pd_7 80 1.13 70 1.13 100 26.49 int1_n na 3.05 na 2.93 na na int3_n na 3.09 na 3.09 na na mc na 24.98 na 45.68 na na
ia 70c20 data sheet 8 - bit microc ontroll er august 19, 2008 i a211030117 - 05 http://w ww.innovasic.com customer support: page 27 of 27 1 - 888 - 824 - 4184 7. 70cx0 errata when in mc mode, bus contents do not match cycle for cycle outside of qualified data times. ie. when ale or enable_n are not active, we do not necessarily match. when in mc mode, our part does not assert rw_n when performing writes to internal registers. oem part does assert rw_n during internal writes, but not consistently. stack addressing ?underflow? or ?under roll? behavior. behavior is different between our part vs. oem when an uneven number of ?pop? operations are done for a given number of ?push? operations. if you ?pop? below register file address 0x00 the oem will stay at 0x00 for the first illegal pop, then go somewhere below 0x00. given ?n? illegal pop operations it will take ?n - 1? push operations to bring stack pointer back to a valid number (0x00). the innovasic d esign will pop down to 0x00 then stop. any push operations after reaching 0x00 will result in incrementing of stack address. register file addressing C when performing an instruction which manipulates two register file locations such as decrement double o n address 0x00 of register file. oem operates on first byte at 0x00, then decrements to 0xff which is not a valid register file location. our part decrements to the top of real physical memory 0x7f. 8. revision history the table below presents the sequence of revisions to document ia211 0 30117 . date revi sion description page(s) august 19, 2008 0 5 corrected control number and reformatted some elements to meet publication standards. na

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